A random access memory (RAM) device generally includes a memory cell array. Exemplary types of random access memory (RAM) devices include, but are not limited to, static RAM (SRAM) devices and dynamic RAM (DRAM) devices. Most memory cell arrays include a plurality of unit memory cells (usually arranged in a matrix form defined by rows and columns, where each of the unit memory cells in a RAM array stores one bit of data), and peripheral circuits that control the input/output of data to/from the unit memory cells. To read data from a memory cell, one of two approaches is commonly used.
Some memory devices implement differential read schemes that use two bitlines to read data from a particular memory cell. In other words, each memory cell within a memory cell array of memory cells is read using a differential pair of bit lines, which therefore requires two bit lines per access port, per column of bits. In some differential read approaches, both bitlines are pre-charged to the same high logic voltage (Vdd), and the memory cell to be read is selected through the same wordline. The memory cell then discharges one of two bitlines depending on its content while keeping the other side high. A differential sense amplifier circuit detects the voltage difference between the two signals on the two bitlines, and latches its value.
Other memory devices implement a single-ended read scheme in which a single bitline is used to read data from a memory cell rather than using a differential pair of bit lines. In a single-ended read scheme, only one of two bitlines is actually used to perform the read operation. After a memory cell is selected via a wordline, the memory cell either holds or discharges the bitlines. A receiver circuit that includes a single-ended sense amplifier circuit is switched after the bitline voltage level drops below a threshold.
Memory devices consume significant power due to their size and the area that they occupy, and power consumption continues to be increasingly important. One technique that is commonly used to reduce power consumption of memory devices is commonly referred to as a “floating bitline” mode of operation or power-saving technique. A memory device operates in floating bit line mode when a read or write operation is not being performed. When a memory device operates in floating bit line mode, pre-charge circuits coupled to the bit lines are turned off and bit lines are left electrically floating to reduce static power consumption.